Use a four-input data selector when a single output line must transmit one signal chosen from several sources. This digital switching element routes one of four input signals to a common output according to the binary state of two control lines. Such selection blocks appear frequently in microprocessor buses, communication paths, and memory addressing logic.
A typical implementation relies on AND, OR, and NOT logic gates. Each input passes through an AND gate combined with a specific control line condition. Two control bits create four combinations: 00, 01, 10, and 11. Only the gate matching the active control state allows its signal to reach the output. The outputs of these gates merge through an OR stage that forwards the chosen data line.
Integrated logic chips such as 74HC153 or 74LS153 provide two independent four-input selectors inside one package. Each block contains four data inputs, two select lines, an enable pin, and a single output. Supply voltage typically ranges from 4.5 V to 5.5 V in TTL variants, while CMOS versions may operate from about 2 V up to 6 V depending on the family.
During design, pay attention to signal propagation delay and fan-out limits. Standard TTL packages show delays around 10–20 ns between input change and output response. If the device drives several logic inputs, verify that total load current remains within the output drive capability listed in the datasheet.
Control line routing determines which input becomes active. When S1=0 and S0=0 the first input reaches the output. Changing the control bits selects the remaining inputs sequentially. This simple switching principle allows several data sources to share a single output path while maintaining clear logical control.
4 to 1 Multiplexer Circuit Diagram With Truth Table and Logic Gate Implementation
Build the four-input data selector using four AND gates, two NOT gates, and one OR gate. Each input line connects to an AND gate that also receives a specific combination of the two select signals. Only one gate becomes active at a time, allowing its signal to pass to the common output node.
Use two control lines labeled S1 and S0. Their binary combinations determine which input reaches the output. When S1=0 and S0=0, input D0 passes through the first AND gate. The combination 01 activates the second path carrying D1. State 10 routes D2, while 11 selects D3. Each gate output joins through a single OR stage that forwards the active signal.
The truth table describing this selection block contains four rows corresponding to the control combinations. Output Y equals the chosen input while the remaining inputs remain electrically blocked by inactive AND gates.
Truth table example: S1=0 and S0=0 → Y=D0. S1=0 and S0=1 → Y=D1. S1=1 and S0=0 → Y=D2. S1=1 and S0=1 → Y=D3.
Discrete logic implementation often uses TTL packages such as 74LS08 for AND operations, 74LS32 for the OR stage, and 74LS04 for signal inversion. Typical propagation delay across the network ranges from 10 ns to 25 ns depending on the logic family.
Keep signal paths short and connect unused inputs to defined logic levels. Floating inputs may produce unstable output states. Stable reference levels maintain predictable operation across the entire digital switching network.
Logic Gate Implementation of a 4 to 1 Multiplexer Using AND OR and NOT Gates
Connect four AND gates to the data inputs D0–D3 and control them with two select lines S1 and S0 plus their inverted forms. Use NOT gates to generate ¬S1 and ¬S0. Each AND gate receives one data input and the specific control combination: D0 with ¬S1·¬S0, D1 with ¬S1·S0, D2 with S1·¬S0, and D3 with S1·S0. Route the outputs of the four AND gates to a single OR gate that produces output Y. Only one path becomes active for each select state, preventing signal overlap.
Implement the logic network with common TTL or CMOS devices. Typical choices include 74LS08 or 74HC08 for the AND functions, 74LS32 or 74HC32 for the OR stage, and 74LS04 or 74HC04 to generate inverted control signals. Maintain short traces between gate outputs and the OR input node to reduce propagation delay and noise pickup. Tie unused gate inputs to defined logic levels to avoid floating states that may cause unstable switching behavior.